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Cadence + Teranetics + X = 10 Gigabit Ethernet
This is the formula that can be used to express the cooperation between the two companies, which will result in the release of a 10 Gigabit Ethernet (10GBASE-T) chip.
Long-standing on the market, Cadence specializes in the development of architectural solutions that are embodied in semiconductor devices; a young company Teranetics aims to produce an advanced element base for high-speed network equipment. What is behind the mysterious letter “X”?
This symbol was chosen to denote the architecture (X Architecture) proposed by Cadence, the essence of which can be summed up in the way the microscopic conductors are oriented inside the chip. In addition to the traditional right-angle conductors (the so-called “Manhattan” way), X involves extensive use of diagonal directions. As a result, the X Architecture can achieve dramatic reduction in die area, improved performance, power consumption and cost savings. All these delights are explained by the fact that the diagonal arrangement of conductors sometimes significantly reduces their length and allows designers to reduce the number of connections between layers.
The architecture is promoted by the X Initiative group, whose members are such large and well-known companies as ARM, ATI Technologies, Canon, Infineon Technologies, Leica Microsystems, Matsushita Electric Industrial, Nikon Corporation, Sanyo Electric, STMicroelectronics, Toshiba Corporation, TSMC, UMC and others.
The use of the X Architecture is expected to significantly reduce the power consumption of the chip for network devices created by Cadence and Teranetics, which will lead to its widespread use.
Source: X Initiative